1. Field of the Invention
The invention in general relates to destructive readout electronic memories, in particular ferroelectric memories, and more particularly to such a memory in which the data cannot be disturbed during power-up, power-down, brownouts and other sub-unstable electronic conditions.
2. Statement of the Problem
Ferroelectric memories are becoming commercially important because they are nonvolatile, can be made at relatively low cost, and can be written to and read at voltages and speeds typical of conventional DRAM and SRAM computer memories; that is, at voltages of from 1 to 5 volts in times of the order of 10 to 100 nanoseconds. See, for example, Orlando Auciello, James F. Scott, and Ramanmoorthy Ramesh, "The Physics of Ferroelectric Memories", Physics Today, Vol. 51, No. Jul. 7, 1998, pp. 22-27. However, these advantages also lead to problems with the memories as compared to other nonvolatile memories. Conventional nonvolatile memories, such as EPROMs, can be written to only by applying relatively high voltages, i.e. 15 volts, for relatively long periods, i.e. 100 microseconds to 200 microseconds. Thus, once they are programmed, the data of EPROMs and other non-ferroelectric nonvolatile memories cannot be disturbed by voltages at which conventional computers operate. However, since ferroelectric memories can be rewritten by relatively short, relatively low voltage pulses, stray voltages, such as can occur during power-up, power-down, and other non-optimal electronic conditions can cause the loss of data.
Most nonvolatile memories, such as EPROMs, EEPROMs, and flash memories, are non-destructive readout memories. In destructive readout volatile memories, such as DRAM, it does not matter whether the data is disturbed on power-up or power-down because, due to their volatility, the systems they are used in expect that data will be lost on power-down.
Present commercial ferroelectric memories utilize a ferroelectric capacitor as the storage medium and an electric field must be placed across the storage capacitor to read it. This reading electric field can alter the state of the memory cell. Thus, ferroelectric memories are destructive read-out memories. See, for example, the memories described in U.S. Pat. No. 5,029,128 issued Jul. 2, 1991 to Haruki Toda, and U.S. Pat. No. 5,406,510 issued Apr. 11, 1995 to Takashi Mihara et. al. Such destructive read-out memories include a rewrite function in which the data read out is restored to the memory cell immediately after it is read. The rewrite function takes time, and if the memory function is truncated, such as by a power loss, while or immediately after a cell is read and before the rewrite cycle can be completed, the data for that cell will be lost. Such data loss is not acceptable for nonvolatile memories. Most commercial memories include power-off and power-on reset functions. The power-off function shuts the system down when the power drops to or below a predetermined voltage, which voltage we shall refer to as the "OFF threshold" voltage. The power-on-reset function resets latches and other resettable circuits when the power rises to or above a predetermined voltage, which voltage we shall refer to as the "ON threshold" voltage. A brownout is an electrical occurrence in which the power drops below the OFF threshold voltage and then immediately comes back up to the ON threshold voltage. If a brownout occurs just as a memory cell is being read and is very short, the power-on-reset function can occur before the rewrite function is finished. In this case, the latches or other multiple state devices that are holding the data to be rewritten can be reset before the data is rewritten. If this occurs, data will be lost. Similarly, data can be lost in other instances when a destructive read-out electronic memory is reset or addressed due to some other non-optimum condition while a memory cell is being read or being rewritten. Brownouts and other unstable conditions that can result in the loss of data occur frequently in certain types of ferroelectric memories. For instance, one important application of ferroelectric memories is in contactless radio frequency identification (RFID) cards. If such an RFID card is being held in a fringe reception area, a number of brownout conditions can occur in a short time leading to loss of significant data.
For the above reasons, it would be highly desirable to have a ferroelectric, destructive read-out electronic memory such that sub-optimum electronic conditions, such as occur on power-up, power-down, and brownouts, cannot cause a loss of data.
3. Solution to the Problem
The present invention solves the above problem by providing a disturb prevention circuit and method that prevents unstable power conditions from disturbing data in the memory cells of a memory system.
In one embodiment, the disturb prevention circuit holds conducting lines in the memory to predetermined voltage states during power-up, power-down, brownouts, and other non-optimal electronic conditions. These predetermined voltage states are such that the probability of data being disturbed at these times is significantly reduced. Preferably, the disturb prevention circuit holds the conducting lines that can carry voltages that can disturb the memory cell at the same voltage, preferably ground, during power-up and power-down.
In another embodiment of the invention, the disturb prevention circuit comprises a delay circuit that delays application of power to the memory array until the control logic is powered up.
In a further embodiment of the invention, the disturb prevention circuit disables a control signal to the memory until the control logic is in a stable electronic state.
In still another embodiment, for a time sufficient to complete the rewrite function, the disturb prevention circuit pauses the logic circuitry that applies signals to the memory array.
In yet another embodiment, a data element holding the data to be rewritten to the memory is frozen for a time sufficient to complete the rewrite function.
The invention provides a destructive readout, nonvolatile memory system comprising: a power source for applying electrical power to the memory system; a destructive readout, nonvolatile memory cell for holding data; and a disturb prevention circuit for preventing the data from being disturbed during a period when the electrical power is unstable.
The invention also provides a ferroelectric memory system comprising: a power source for applying electrical power to the memory system; a memory cell for holding data, the memory cell including a ferroelectric material; and a disturb prevention circuit for preventing the data from being disturbed during a period when the electrical power is unstable. Preferably, the period is selected from the group consisting of a power-up period, a power-down period, and a brownout period. Preferably, the disturb prevention circuit comprises a circuit for preventing disturb voltages from being applied to the memory cell during the period. Preferably, the memory includes: a circuit for reading the data and rewriting the data to the memory cell after it has been read; and the disturb prevention circuit comprises a circuit for preventing loss of the data before it is rewritten. Preferably, the memory includes a conductor directly electrically connected to or directly electrically connectable to the memory cell, and the disturb prevention circuit comprises a clamping circuit for clamping the conductor to a predetermined voltage. Preferably, there are two of the conductors, the two of the conductors comprise a bit line and a word line, and the disturb prevention circuit comprises a circuit for clamping the word line and the bit line to the predetermined voltage. Preferably, the voltage is the memory system ground. Preferably, the memory cell is part of an array of memory cells, the memory system further includes a logic circuit for applying signals to the array of memory cells and a power supply for applying power to the logic circuit and the memory array, and the disturb prevention circuit comprises a circuit for applying power to the logic circuit prior to applying power to the memory array. Preferably, the memory cell is part of an array of memory cells, the memory system further includes a logic circuit for applying signals to the array of memory cells and a power supply for applying power to the logic circuit and the memory array, and the disturb prevention circuit comprises a delay circuit for delaying the application of power from the power supply to the memory array for a period of time sufficient to permit the logic circuit to become operational before power is applied to the memory array. Preferably, the memory system comprises an electrical line for applying a control signal within the memory system and the disturb prevention circuit comprises a disable circuit for disabling the control signal for a predetermined time. Preferably, the period is a power-up period and the predetermined time includes the power-up period. Alternatively, the period is a power-down period and the predetermined time includes the power-down period. Preferably, in another alternative, the period is a brownout period and the predetermined time includes the brownout period. Preferably, the memory includes logic for applying a voltage signal to the memory cell, the period is a power-up period, and the predetermined time is a time sufficient to permit the logic to become operational. Preferably, the disable circuit includes a one-shot pulse generator circuit. Preferably, the disable circuit includes a latch. Preferably, the memory includes a logic circuit and the disable circuit includes a reset circuit for producing a reset signal for resetting the logic circuit. Preferably, the memory comprises a radio frequency identification card memory. Preferably, the memory includes a memory array and a logic circuit for applying a signal to the memory array, the cell is part of the memory array, and the disturb prevention circuit comprises a pause circuit for producing a pause signal for causing the logic circuit to pause during a predetermined time. Preferably, the logic circuit includes a timing generator responsive to the pause signal for pausing during the predetermined time. Preferably, the period is a brownout period and the predetermined time includes the brownout period. Preferably, the memory includes: a circuit for reading the data and rewriting the data to the memory cell after it has been read; and the predetermined time comprises a time sufficient to complete the rewriting of the data. Preferably, the disturb prevention circuit comprises a circuit for providing a freeze signal. Preferably, the memory includes a memory array and the memory cell is part of the memory array, the memory further includes a data storage element for holding data to be rewritten to the memory array, and a freeze circuit responsive to the freeze signal for preventing the state of the data storage element from changing.
In another aspect, the invention provides a ferroelectric memory system comprising: a memory cell; and a disturb prevention circuit for preventing disturb voltages from being placed on the memory cell during a period selected from the group consisting of a power-up period, a power-down period, and a brownout period.
In another aspect, the invention provides a destructive readout memory system comprising: a destructive readout memory cell; and a disturb prevention circuit for preventing disturb voltages from being placed on the memory cell during a period selected from the group consisting of a power-up period, a power-down period, and a brownout period. Preferably, the condition is selected from the group consisting of a power-up condition, a power-down condition, a brownout condition. Preferably, the condition is selected from the group consisting of the power-down condition and the brownout condition; the memory system comprises a logic circuit for writing, reading, and rewriting data into the memory cell; and the disturb prevention circuit comprises a circuit communicating with the logic circuit for preventing the rewriting of the data from being disturbed due to the condition.
In a further aspect, the invention provides a ferroelectric memory system comprising: a power source for applying electrical power to the memory system; a memory cell for holding data, the memory cell including a ferroelectric material; and a disturb prevention circuit for preventing the data from being disturbed due to a condition in which the electrical power is unstable. Preferably, the condition is elected from the group consisting of a power-up condition, a power-down condition, brownout condition. Preferably, the condition is selected from the group consisting the power-down condition and the brownout condition; the memory system comprises a logic circuit for writing, reading, and rewriting data into the memory cell; and the disturb prevention circuit comprises a circuit communicating with the logic circuit for preventing the rewriting of the data from being disturbed due to the condition. Preferably, the logic circuit includes a data storage device for storing data to be rewritten into the memory cell, and the disturb prevention circuit comprises a circuit for preventing the loss of the data in the data storage device due to the condition. Preferably, the power source comprises a source of a voltage; the memory system further includes a memory array and the memory cell is part of the memory array; the memory system further includes a logic circuit for applying an electrical signal to the memory array and a power-on-reset circuit for resetting the logic circuit when the voltage drops below an OFF threshold then rises to an ON threshold; and the disturb prevention circuit comprises a circuit for preventing the resetting of the logic circuit from causing loss of the data. Preferably, the source of a voltage includes a circuit for producing the voltage from a radio frequency source. Preferably, the logic circuit includes a timing signal generator and the disturb prevention circuit comprises a pause signal generating circuit for generating a pause signal for preventing the timing signal generator from outputting signals that could result in loss of the data. Preferably, the pause signal generating circuit comprises a circuit for generating the pause signal for a predetermined time. Preferably, the logic circuit includes a state machine and the disturb prevention circuit comprises a circuit for inhibiting the state machine from outputting signals that could result in loss of the data. Preferably, the memory system includes a data storage element and a freeze circuit for freezing the data content of the data storage element while a predetermined signal is applied to the freeze circuit. Preferably, the disturb prevention circuit consists essentially of transistors, inverters, and other electronic elements that operate reliably at voltages significantly less than the supply voltage of the memory system. Preferably, the memory system further includes a circuit for producing a system supply voltage from a radio frequency source. Preferably, the disturb prevention circuit comprises a circuit for preventing disturb voltages from being applied to the memory cell due to the condition.
In still another aspect, the invention provides a method of operating a destructive readout, nonvolatile memory having a memory cell in which data is stored, the method comprising the steps of: sensing a low power condition of the memory; and preventing unintended voltages produced by the low power condition from disturbing the data in the memory cell.
The invention also provides a method of operating a ferroelectric memory having a memory cell in which data is stored, the method comprising the steps of: sensing a low power condition of the memory; and preventing unintended voltages produced by the low power condition from disturbing the data in the memory cell. Preferably, the memory includes a conductor directly connected to or directly connectable to the memory cell and the step of preventing comprises clamping the conductor to a predetermined voltage. Preferably, the memory includes a logic circuit for applying a logic signal to the memory cell, and a memory array, the memory cell being part of the memory array; and the step of preventing comprises directing power to the logic circuit, and then after the logic circuit has reached an operating voltage, directing power to the memory array. Preferably, the step of preventing comprises: receiving a memory control signal; and disabling the memory signal for a time period in which the low power condition could cause the unintended voltages. Preferably, the memory includes a logic circuit for applying a signal to the memory cell, and the step of preventing comprises stopping the operation of the logic circuit for a time period in which the low power condition could cause the unintended voltages.
In another aspect, the invention provides a method of operating a destructive read out memory having a destructive readout memory cell in which data is stored, the method comprising the steps of: reading the data in the memory cell; rewriting the data to the memory cell; sensing a low power condition in the memory; and preventing the low power condition from disturbing a step selected from the group consisting of the reading step and the rewriting step. Preferably, the memory includes a logic circuit, and the step of preventing comprises freezing the logic circuit for a time sufficient to complete the rewriting the data to the memory cell.
In addition, the invention provides a method of operating a ferroelectric memory having a ferroelectric memory cell in which data is stored, the method comprising the steps of: reading the data in the ferroelectric memory cell; rewriting the data to the ferroelectric memory cell; sensing a low power condition in the memory; and preventing the low power condition from disturbing a step selected from the group consisting of the reading step and the rewriting step. Preferably, the memory includes logic circuit, and the step of preventing comprises freezing the logic circuit for a time sufficient to complete the rewriting the data to the memory cell.
The memory according to the invention not only prevents loss of data during power-up, power-down, brownouts and other non-optimum operating conditions, but also does this simply and economically and without introducing further potential data loss mechanisms into the memory system. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.